# these are the sources - everything depends upon them
RTL=$(wildcard hdl/*/*.vhd) $(wildcard hdl/top/*.vhd)
XDC=$(wildcard xdc/*.xdc)

# these are all basic compilation targets, starting with "all"
all: setup synth
full: setup synth impl gen_bit

# target to create the project file for the top level project
setup: work/top/top.xpr
work/top/top.xpr:
	@echo " === creating project === "
	mkdir -p work
	vivado -mode batch -source scripts/setup.tcl -nolog -nojournal

synth: $(RTL) $(XDC)
	@echo " === synthesizing === "
	vivado -mode batch -source scripts/synth.tcl -nolog -nojournal || (echo " === SYNTH STEP ERROR SUMMARY === "; cat work/top/top.runs/synth_1/runme.log | tail -n +21; exit 1)

impl: synth
	@echo " === implementing === "
	vivado -mode batch -source scripts/impl.tcl -nolog -nojournal || (echo " === IMPL STEP ERROR SUMMARY === "; cat work/top/top.runs/impl_1/runme.log | tail -n +21; exit 1)

gen_bit: impl
	@echo " === generating bitstream === "
	vivado -mode batch -source scripts/generate_bitstream.tcl -nolog -nojournal


# target to program the target FPGA
work/top/top.bit: gen_bit
program_target: work/top/top.bit
	@echo " === programming target === "
	vivado -mode batch -source scripts/program_target.tcl -log work/program_target.log -jou work/program_target.jou

# target to execute sim without the gui
sim: compile
	@echo " === running sim === "
	vivado -mode batch -source scripts/sim.tcl -log work/sim.log -jou work/sim.jou || (echo " === SIM STEP ERROR SUMMARY === "; cat work/top/top.sim/sim_1/behav/xsim/xvhdl.log)

# target to launch the gui
gui: setup
	@echo " === opening gui === "
	vivado -mode gui -source scripts/gui.tcl -log work/gui.log -jou work/gui.jou &

# target to execute sim with the gui
gui_sim: compile
	@echo " === running sim in gui === "
	vivado -source scripts/sim.tcl -nolog -nojournal

# delete all work related files
clean:
	@echo " === cleaning project === "
	rm -rf work

.PHONY: all full setup synth impl gen_bit gui_sim gui program_target clean
